NAND type EEPROMs (Electrically Erasable Programmable Read Only Memories) or FLASH memories have been considered as a replacement for hard disk drives (HDDs). It is therefore desired that these devices have larger capacities, lower cost, and reduced cell size for miniaturization and increased processing speed.
U.S. Pat. No. 5,050,125 (the '125 Patent) discloses a non-volatile semiconductor memory where each bit line comprises a series array of FLASH memory cells (shown in the cross-sectional view of FIG. 4 of the '125 Patent). Cell size or area is defined by the width of the floating gate and adjacent insulating region (X-direction of FIG. 4) by the width of the associated control gate and adjacent insulating region (in the Y-direction), i.e., the overlapping area needed for the floating gate and control gates. The cell size of each cell of the '125 Patent cannot be reduced beyond about 4F2-5F2, where “F” is the minimum feature size or line width obtainable by a lithography technique used in the manufacturing process of the '125 Patent. This minimum feature size is believed to be currently about 90 nm. This conclusion assumes that the minimum width of the floating gate is about 1F and the minimum width of the spacing between adjacent floating gates in an array of floating gates is also about 1F, while the minimum width of the control gate is about 1F and the minimum spacing between adjacent control gates is about 1F, meaning each cell occupies at least a minimum of 2F in the X-direction and 2F to 2.5 F in the Y-direction.
It would be desirable to increase the integration density of FLASH memory arrays. Therefore, it is desired to provide a FLASH memory cell having a cell size that is not limited by the minimum line width that can be produced by lithography techniques used in the manufacturing of the FLASH device.